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CPU cache
Results: 1614

#	Item
751	Positional Adaptation of Processors: Application to Energy Reduction ∗ Michael C. Huang Jose Renau and Josep Torrellas Dept. of Electrical and Computer Engineering Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2003-04-01 22:17:30 Subroutines Cache Holism Source code University of Cambridge Computer Laboratory Call stack CPU cache Parameter Algorithm Software engineering Computing Computer programming
752	IBM Research HPC Challenge 2005 Awards Competition: UPC on BlueGene/L C. Caşcaval, C. Barton, G. Almási, Y. Zheng, M. Farreras, P. Luk, R. Mak Add to Reading List Source URL: www.hpcchallenge.org Language: English - Date: 2005-12-01 12:52:33 Lawrence Livermore National Laboratory Parallel computing Power Architecture IBM CPU cache K computer HPC Challenge Benchmark Computing Computer hardware Blue Gene
753	RelaxReplay: Record and Replay for Relaxed-Consistency Multiprocessors Nima Honarmand and Josep Torrellas University of Illinois at Urbana-Champaign {honarma1,torrella}@illinois.edu http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-01-10 19:23:01 Computing Parallel computing Instruction set CPU cache Microarchitecture Processor register Linearizability MIMD Computer architecture Computer hardware Central processing unit
754	Prototyping Architectural Support for Program Rollback Using FPGAs ∗ Radu Teodorescu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign {teodores,torrellas}@cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-05-11 13:27:29 Computer engineering CPU cache Microarchitecture Speculative execution Processor register Application checkpointing Parallel computing Instruction set Multithreading Computer architecture Computer hardware Central processing unit
755	USING AN ADAPTIVE HPC RUNTIME SYSTEM TO RECONFIGURE THE CACHE HIERARCHY SC’14, Nov. 20, 2014 Ehsan Totoni, Josep Torrellas, Laxmikant V. Kale Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-12-19 19:14:48 Central processing unit Ø Slashed zero Numbers Information Computer memory Cache CPU cache
756	SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization ∗ James Tuck‡ ‡ NC State University Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-08-20 21:14:12 Software optimization Software engineering Data types Primitive types Memoization CPU cache Lookup table Memory disambiguation Pointer Computing Computer programming Computer performance
757	Illusionist: Transforming Lightweight Cores into Aggressive Cores on Demand Amin Ansari University of Illinois [removed] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-01-25 16:46:06 Central processing unit Microprocessors Instruction set architectures Parallel computing DEC Alpha CPU cache Branch predictor Multithreading ARM architecture Computer architecture Computer hardware Computing
758	BulkCommit: Scalable and Fast Commit of Atomic Blocks ∗ in a Lazy Multiprocessor Environment † Xuehai Qian , Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-10-25 19:56:50 Computer file formats Graphics file formats Cache coherency Chunk CPU cache MESI protocol ANIM Parallel computing C dynamic memory allocation Computing Computer memory Computer hardware
759	DECchip[removed]and DECchip[removed]Core Logic Chipsets Data Sheet Order Number: EC–QAEMB–TE Revision/Update Information: Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:54 Instruction set architectures Computer memory Alpha 21064 Computer buses Minicomputers DEC Alpha Conventional PCI CPU cache VAX Computer hardware Computer architecture Computing
760	Software Logging under Speculative Parallelization ´ Garzar´an, Milos Prvulovicy , Jos´e Mar´ıa Llaber´ıaz , Mar´ıa Jesus ˜ V´ıctor Vinals, Lawrence Rauchwergerx , and Josep Torrellasy Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2001-09-30 19:59:18 Central processing unit Parallel computing Microprocessors Computer memory CPU cache Microarchitecture Cache Automatic parallelization Superscalar Computer hardware Computer architecture Computing

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